A semiconductor wafer fragment 10 comprising a prior art capacitor construction is illustrated in FIG. 1. Wafer fragment 10 comprises a substrate 12. Substrate 12 can comprise, for example, a monocrystalline silicon wafer lightly doped with a conductivity-enhancing dopant. To aid in interpretation of the claims that follow, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
An insulative material layer 14 is formed over substrate 12. Layer 14 can comprise, for example, borophosphosilicate glass (BPSG). An electrical node 16 is formed within substrate 12. Node 16 can 1 comprise, for example, a diffusion region formed by implanting conductivity-enhancing dopant within substrate 12.
An opening extends through layer 14, and a container-type capacitor assembly 20 extends within the opening. Capacitor assembly 20 comprises a storage node 18, a dielectric layer 22, and a capacitor plate 24. Storage node 18 can comprise, for example, conductively-doped rugged polysilicon, wherein rugged polysilicon is defined to encompass hemispherical grain polysilicon and cylindrical grain polysilicon. Dielectric layer 22 typically comprises a composite of silicon oxide and silicon nitride. Capacitor plate 24 typically comprises conductively-doped polysilicon. Storage node 18 is in electrical connection with electrical node 16.
A difficulty in forming capacitor assembly 20 arises in forming storage node 18. Formation of storage node 18 typically comprises providing conductively-doped hemispherical grain polysilicon within the opening and over layer 14. The hemispherical grain polysilicon is subsequently etched to leave the hemispherical grain polysilicon remaining only in the opening. During such etching, conductive polysilicon particulates can be formed. Such particulates can redeposit on wafer 10 to cause shorts in an integrated circuit formed on wafer 10. For instance, it is common in semiconductive processing to form multiple capacitor assemblies 20 on a single semiconductive wafer. Conductive polysilicon particles formed during etching of a hemispherical grain polysilicon layer can redeposit between adjacent capacitor structures to form a short between the capacitor structures. It would be desirable to develop alternative methods for forming a capacitor structure wherein a hemispherical grain polysilicon layer is etched to form a storage node without having conductive polysilicon particles redepositing and shorting electrical components.